1. Field of the Invention
The present invention relates to IC testers for testing the electrical characteristics of an IC (Integrated Circuit), and more particularly to an IC tester that can set a plurality of test conditions.
2. Description of the Background Art
In accordance with increase in the integration density and incorporation of multifunctions in an IC, the circuit complexity and the number of input and output terminals have been increased. The time required for testing the electrical characteristics of such an IC is getting longer since measurement covering a great number of items must be taken. In general, an IC tester is widely used for testing an IC. The performance of the IC tester will greatly contribute to reduce the time required for testing.
FIG. 1 is a block diagram showing a schematic structure of a conventional IC tester. The IC tester includes an CPU (Central Processing Unit) 1 for providing the overall control of the IC tester, a reference signal generation circuit 2 for generating a reference signal used in forming a test waveform, a control circuit 3 for controlling each circuit in testing an IC 12 of interest, a reference signal delay circuit 4 for delaying the reference signal generated by reference signal generation circuit 2, a test pattern storage circuit 5 for storing a test pattern of under-testing IC 12, a delay amount storage circuit for storing the amount of delay by reference signal delay circuit 4, a test waveform formation circuit 7 for forming a test waveform according to signals output from reference signal delay circuit 4 and test pattern storage circuit 5, a voltage amplify circuit 8 for amplifying the voltage of the signal output from test waveform formation circuit 7, a voltage supply circuit 9 for supplying a voltage to voltage amplify circuit 8, a D/A (digital/analog) conversion data storage circuit 10 for holding input data and providing the data to voltage supply circuit 9, and a control signal transmission bus 13 that is used by CPU 1 in providing data to respective circuits. In testing IC 12, control circuit 13 provides an address 14 to test pattern storage circuit 5 and delay amount storage circuit 6.
FIG. 1 depicts the schematic structure of one channel for the IC tester. The IC tester includes a plurality of the circuitry shown in FIG. 1. In testing IC 12, CPU 1 sets the data for test pattern storage circuit 5, delay amount storage circuit 6 and D/A conversion data storage circuit 10 for each channel.
The process of forming a test waveform input to under-testing IC 12 will be described hereinafter. CPU 1 includes an internal memory for storing a test program according to the test specification of under-testing IC 12 and test conditions. CPU 1 executes the test program to generate a test waveform according to a plurality of test items. The generated test waveform is provided to under-testing IC 12. For example, CPU 1 has all the test patterns required for testing prestored in test pattern storage circuit 5 when testing is to be carried out. In executing the first test item, CPU 1 has the amount of delay corresponding to the time from the transition of the reference signal until the transition of the test waveform stored for each test pattern in delay amount storage circuit 6. The voltage value of that output waveform is stored in D/A conversion data storage circuit 10. Then, the test is initiated. In general, CPU 1 has the data for executing the next test item stored in delay amount storage circuit 6 and D/A conversion data storage circuit 10 after the test of the previous test item is completed.
Reference signal generation circuit 2 generates a reference signal for testing IC 12. The cycle of a reference signal corresponds to the cycle of the test waveform generated by test waveform formation circuit 7.
Test pattern storage circuit 5 holds the test pattern of the test item stored by CPU 1. When IC 12 is tested, a test pattern is sequentially provided to test waveform formation circuit 7 in synchronization with the change of address signal 14 applied from control circuit 3.
Delay amount storage circuit 6 holds the amount of delay stored by CPU 1. When IC 12 is tested, the amount of delay is provided to reference signal delay circuit 4 in synchronization with the change in address signal 14 output from control circuit 3. The details of delay amount storage circuit 6 will be described afterwards. Reference signal delay circuit 4 delays the reference signal output from reference signal generation circuit 2 in a programmable manner according to the amount of delay from delay amount storage circuit 6. The delayed signal is provided to test waveform formation circuit 7.
Test waveform formation circuit 7 holds the test pattern output from test pattern storage circuit 5 in synchronization with the delayed reference signal output from reference signal delay circuit 4. The output of test waveform formation circuit 7 is provided to voltage amplify circuit 8.
D/A conversion data storage circuit 10 holds and provides to voltage supply circuit 9 the digital data stored by CPU 1. Voltage supply circuit 9 converts the digital data into an analog voltage value, which is provided to voltage amplify circuit 8. Voltage amplify circuit 8 amplifies the voltage of the test waveform output from test waveform formation circuit 7 according to the analog voltage value from voltage supply circuit 9. The amplified voltage is provided to under-testing IC 12.
When the IC tester is executing one test item, CPU 1 issues a control signal via transmission bus 13 to store data into test pattern storage circuit 5, delay amount storage circuit 6, and D/A conversion data storage circuit 10. Then, CPU 1 sends to control circuit 3 an instruction to initiate testing of IC 12. Control circuit 3 responds to this instruction from CPU 1 to increment address signal 14 provided to test pattern storage circuit 5 and delay amount storage circuit 6 in synchronization with a reference signal output from reference signal generation circuit 2. Test pattern storage circuit 5 and delay amount storage circuit 6 sequentially provide the test pattern and delay amount corresponding to address signal 14, respectively. Test waveform formation circuit 7 produces a test waveform according to the delayed reference signal from reference signal delay circuit 4 and the test pattern from test pattern storage circuit 5. The test waveform is provided to voltage amplify circuit 8. Here, delay amount storage circuit 6 and D/A conversion data storage circuit 10 are referred to as "test condition storage circuit", and test waveform formation circuit 7 and voltage amplify circuit 8 are referred to as "waveform formation circuit".
By sequentially carrying out the above process for each test item, the testing operation on IC 12 is carried out. In general, D/A conversion data storage circuit 10 continuously outputs the data set by CPU 1 prior to the test until the entire test is completed.
FIG. 2 is a block diagram showing a specific structure of delay amount storage circuit 6 of FIG. 1. Delay amount storage circuit 6 includes a pointer storage circuit 20 storing the pointer used in selecting an amount of delay, and a delay amount storage table 21 for storing the amount of data that is provided to reference signal delay circuit 4 and three-state buffers 22 and 23.
Delay amount storage circuit 6 is taken as an example to be described hereinafter of the storage circuits such as delay amount storage circuit 6 and D/A conversion data storage circuit 10 that has data updated rather frequently.
A plurality of delay amount data that will be used by reference signal delay circuit 4 are stored in delay amount storage table 21 by CPU 1. The pointer of the delay amount data stored in delay amount storage table 21 is stored in pointer storage circuit 20 by CPU 1. Pointer storage circuit 20 has a capacity that can store data identical to the number of test patterns stored in test pattern storage circuit 5. Data corresponding to address signal 14 output from control circuit 3 is provided to delay amount storage table 21 as the pointer.
In storing data into pointer storage circuit 20, CPU 1 renders the output of three-state buffer 22 to a high impedance state. Three-state buffer 23 is turned on. In response, the data from CPU 1 is provided to pointer storage circuit 20. CPU 1 stores data into pointer storage circuit 20 by sequentially changing the address of pointer storage circuit 20 via control circuit 3.
In storing data into delay amount storage table 21, CPU 1 renders three-state buffer 23 to a high impedance state. Three-state buffer 22 is turned on. In response, the address from control circuit 3 is provided to delay amount storage table 21. CPU 1 sequentially stores data by applying the address to delay amount storage table 21 via control circuit 3.
In testing IC 12, the pointer corresponding to address signal 14 output from control circuit 3 is provided from pointer storage circuit 20. The amount of delay selected by that pointer in delay amount storage table 21 is provided to reference signal delay circuit 4. Delay amount storage table 21 accommodates a plurality of types of ICs such as an IC 1 that requires four delay amount data and an IC 2 that requires N delay amount data as shown in FIG. 2 since the number of the delay amount to be set depends upon the type of the IC to be tested.
FIGS. 3A-3D are diagrams for describing the procedure of forming a waveform in a conventional IC tester. According to the delay amount output from delay amount storage circuit 6 shown in FIG. 3A, reference signal delay circuit 4 delays the reference signal of FIG. 3B to the signal shown in FIG. 3C. Test waveform formation circuit 7 holds the test pattern output from test pattern storage circuit 5 with the delayed reference signal, which is output as a test waveform shown in FIG. 3D.
The IC tester must carry out a test item corresponding to various test conditions for the purpose of testing the electrical properties of an IC of interest. These test conditions are reset for each test item. The time required for resetting the test conditions is great for an IC that has a complex function. In practice, an IC tester has a plurality of the circuitry shown in FIG. 1 corresponding to one channel. Since it is necessary to reset the test conditions for each circuitry, the amount of data for the reset operation is great. There was a problem that the time required for resetting the test conditions occupied a major portion of the IC testing time.